The present invention relates generally to the manufacture of semiconductor devices, and more particularly to a method of enclosing a metal via in a dual damascene process.
Damascene processes are widely used in the manufacture of semiconductor devices. Generally, in a damascene process, a dielectric layer is first deposited on a substrate, a portion of the dielectric layer is then removed by an etching process in accordance with a mask pattern, the etched areas in the dielectric layer are lined with a barrier metal and then filled with a metal, and finally the excess liner and metal deposited over the dielectric layer is removed in a planarization process. By this method, metal features such as vias or lines are formed on a substrate.
Typically, vias and lines are formed in separate damascene processes, known as single damascene. For example, to form a layer of metal lines on a substrate, a dielectric layer is first deposited, then a portion of the dielectric layer is etched according to a mask pattern which corresponds to the desired line pattern, a metal liner is then deposited on the dielectric layer and in the etched line areas in the dielectric layer, these etched line areas are then filled with a metal, and finally the excess metal and liner on top of the dielectric layer is removed in a planarization process. A layer of vias are formed in a similar process, except that the mask pattern corresponds to the desired via pattern. Thus, to form a layer of vias and lines, two metal fill steps and two metal planarization steps are required.
In the electronics industry, there is a current trend toward using more cost effective dual damascene in the fabrication of interconnection structures. In a dual damascene process, both the via and the line are formed in the same damascene process. To form the via and the line in the same damascene process, a thicker dielectric layer is first deposited on a substrate, the dielectric layer is then etched according to a mask pattern which corresponds to both the desired via pattern and the desired line pattern, a liner is then deposited on the dielectric layer and in the etched areas in the dielectric layer, these etched areas are then filled with a metal, and the excess metal and liner is removed by a planarization process. This dual damascene process therefore reduces the number of costly metal fill and planarization steps.
However, recent studies have shown that interconnection structures formed using a dual damascene process are susceptible to failure caused by electromigration effects. FIG. 1 illustrates a cross sectional view of a wafer stack 100 formed using a conventional dual damascene process. The wafer stack 100 includes a substrate 102, an oxide layer 104, a metal layer 106, a dielectric layer 108, a liner 110, a metal via 112 and a metal line 114. The metal via 112 and metal line 114 are formed by a dual damascene process in which the dielectric layer 108 is first deposited on top of the metal layer 106, the dielectric layer 108 is then etched to form via 112 and trench 114 according to a mask pattern which defines the desired line and via pattern, the liner 110 is deposited on the dielectric layer 108 and in the etched portions of the dielectric layer 108, a metal is then deposited in the via 112 and trench 114, and finally the excess metal and liner on top of the dielectric layer 108 are removed by a planarization process.
In this wafer stack configuration, when an electric potential is applied across the metal via 112 and metal line 114, the electric potential causes an electromigration effect in the metal via 112 and metal line 114. Specifically, the electric potential causes one portion of the interconnect structure to be a cathode and the other portion to an anode. The electric potential between the cathode and the anode causes a current flow from the anode end to the cathode end through metal via 112 and metal line 114. Since the direction of electrons is opposite of the direction of current flow, the electrons migrate from the cathode end of the metal via 112 toward the anode end of the metal line 114. In this process, the moving electrons generate an xe2x80x9celectron windxe2x80x9d which pushes or forces the metal atoms in the direction of the electrons from the metal via 112 near the cathode to the metal line 114 near the anode. The liner 110 prevents the electrons and atoms in the metal layer 106 from migrating to the metal via 112 and metal line 114. As a result, a void 116 forms near the cathode in the metal via 112. The formation of this void often leads to catastrophic failure of the device. The failure is catastrophic because the liner 110 at the bottom of the via 112 is often thinner than in the line and therefore is unable to shunt the current across the void.
Void formation due to electromigration is a well known phenomenon. Several methods have been proposed to counteract this electromigration effect in interconnects and thereby prevent void formation. For example, in IBM Technical Disclosure Bulletin Vol. 31, No. 6 (1988), tungsten (W) links are interposed periodically in long aluminum-copper (Al-Cu) lines or minimum groundrule features interfacing contact pads. These tungsten links form a physical barrier to the Al-Cu atoms being transported between the cathode to the anode. As another example, U.S. Pat. No. 5,470,788 to Biery et al. proposes interposing segments of Al with segments of refractory metal such as W.
Each of these methods utilize the xe2x80x9cshort-length effect.xe2x80x9d The short-length effect takes place in short interconnections if an electrical current is supplied through leads of materials in which the diffusivity of the interconnection metal is low. The physical origin of the short-length effect is the build-up of backstress. As interconnection metal atoms pile up against the diffusion barrier leads, this backstress counteracts the electromigration driving force. A steady-state condition arises in situations where the backstress exactly balances the electromigration driving force. Under this condition, no further electromigration damage occurs.
The existence of the short-length effect has been demonstrated by several investigators, such as by H. V. Schreiber in the article xe2x80x9cElectromigration Threshold of Aluminum Filmsxe2x80x9d published in Solid State Electronics, Vol. 28, No. 6, p. 617; by R. G. Filippi et al., in the article xe2x80x9cEvidence of the Electromigration Short-Length Effect in Aluminum Based Metallurgy with Tungsten Diffusion Barriersxe2x80x9d published in the Proceedings of the Materials Research Symposium, Vol. 309, pp. 141-148,; and by X. X. Li et al., in the article xe2x80x9cIncrease in Electromigration Resistance by Enhancing Backflow Effectxe2x80x9d published in the Proceedings of the 30th International Reliability Physics Symposium, March 1992, p. 211.
The short-length effect has been used advantageously to reduce the electromigration effect in via-line interconnects by enclosing or encapsulating the via. For example, U.S. Pat. No. 6,054,378 to Skala et al. (xe2x80x9cSkalaxe2x80x9d) discloses a method for encapsulating a metal via in a damascene process. The encapsulation of the metal via with a conductive barrier layer prevents the electromigration of interconnect metal atoms from the via to the line and thereby prevents voiding at the bottom of the via.
Although the method disclosed in the Skala patent is described as a dual damascene process, an examination of the process steps reveals that the via and line actually are formed in two single damascene processes. Referring to FIGS. 2A-2I of Skala, the via is formed, encapsulated, filled and planarized in the single damascene process depicted in FIGS. 2B-2E. Then the trench is formed, encapsulated, filled and planarized in a second single damascene process depicted in FIGS. 2F-2I. As discussed previously, a dual damascene process is more cost effective because the metal fill and planarization steps are performed only once. Therefore, there is a need in the art for a method of enclosing a via using a dual damascene process.
In the formation of a semiconductor device interconnect, it is often desirable to form the via prior to forming the trench. Forming the via first may be desirable because the via lithography and anti-reflective coating (ARC) etch are carried out on a planar surface, which is advantageous because the via lithography has a smaller process window than the line lithography. The ARC and photoresist for the line lithography then fills in the via holes, providing a fairly planar surface for the line lithography.
There are also advantages to forming the trench prior to forming the via. When the via is formed first, etch residues accumulate along the via sidewalls. These etch residues are derived from organic material from the line lithography which forms hardened polymers when subjected to the line etch chemistry. As dimensions shrink, it becomes increasingly difficult to adequately clean the etch residues from the very small and relatively deep vias. By forming the trench first, etch residues are more easily removed from the relatively shallow trench.
In the Skala method, the via must be formed prior to the line. If the line is formed first using the single damascene process described in the Skala patent, then the via cannot be formed in a subsequent second single damascene process for two reasons. First, if the via photomask is positioned such that the via is superimposed over the line, then the metallized line and barrier layer must be etched prior to etching the underlying dielectric layer. The conditions required for etching of a metallized line and barrier layer are impractical for many fill and barrier metals. For example, there is no known etching process that will reliably etch through copper as the bulk fill metal.
Alternatively, if the via photomask is positioned such that the via is adjacent to the barrier layer of the line, etching of the line metal and barrier layer metal is no longer necessary. However, this scenario relies on an overlay tolerance in the photolithography process used to form the via which is unachievable in present-day processes. In semiconductor devices with line widths or via diameters of about 0.1 xcexcm to about 1 xcexcm, the barrier layer is only about 10 xc3x85 to about 1000 xc3x85 thick. Thus, the error in photomask alignment must be substantially less than this range of 10-1000 xc3x85. This degree of overlay tolerance is unachievable using present-day photolithography processes. Therefore, there is a need in the art for a robust method of enclosing a via, in which either the line or the via can be formed first.
In accordance with the present invention, a process is disclosed for enclosing a via in a semiconductor device. This process includes a dual damascene process wherein the via and the trench are filled in the same metallization step. Moreover, with this process, either the via or the trench can be formed first.
In one aspect of the present invention, the process of enclosing a via comprises the steps of: (a) forming a dielectric layer over a first metal layer, wherein the dielectric layer has a thickness; (b) forming a via in the dielectric layer, wherein the via has a depth at least equal to the thickness of the dielectric layer, thereby defining a sidewall of the dielectric layer and exposing a portion of the first metal layer; (c) conformally depositing a first metal liner in the via, wherein the first metal liner includes a bottom portion deposited over the exposed portion of the first metal layer and a sidewall portion deposited over the sidewall of the dielectric layer; (d) forming at least one trench in the dielectric layer adjacent to the first metal liner, wherein the trench has a depth less than the thickness of the dielectric layer, thereby defining a trench bottom and a trench sidewall and exposing an upper portion of said sidewall portion of the first metal liner; (e) conformally depositing a second metal liner in the trench, wherein at least a portion of the second metal liner is deposited over the trench bottom and over the trench sidewall; and (f) depositing a second metal layer over the first metal liner and the second metal liner, wherein the second metal layer substantially fills the via and the trench.
In another aspect of the present invention, the process for enclosing a via comprises the steps of: (a) forming a dielectric layer over a first metal layer, wherein the dielectric layer has a thickness; (b) forming a partial via in the dielectric layer, wherein the partial via has a depth less than the thickness of the dielectric layer, thereby defining a partial via bottom and a partial via sidewall; (c) conformally depositing a first metal liner in the partial via, wherein the first metal liner includes a sidewall portion deposited over the partial via sidewall; (d) forming at least one trench in the dielectric layer adjacent to the first metal liner, wherein the trench has a depth less than the thickness of the dielectric layer, thereby defining a trench sidewall and a trench bottom and exposing a portion of said sidewall portion of the first metal liner; (e) forming a full via in the dielectric layer which comprises the partial via and a portion extending from the partial via bottom to the first metal layer, wherein the full via has a depth at least equal to the thickness of the dielectric layer, thereby defining a via sidewall of the dielectric layer and exposing a portion of the first metal layer; (f) conformally depositing a second metal liner in the trench and in the full via, wherein at least a portion of the second metal liner is deposited over the trench sidewall and the trench bottom, over said via sidewall of the dielectric layer, and over said exposed portion of the first metal layer; and (g) depositing a second metal layer over the first metal liner and second metal liner, wherein the second metal layer substantially fills the trench and the full via.
In yet another aspect of the present invention, the process for enclosing a via comprises the steps of: (a) forming a dielectric layer over a first metal layer, wherein the dielectric layer has a thickness; (b) forming a trench in the dielectric layer, wherein the trench has a depth less than the thickness of the dielectric layer, thereby defining a trench bottom and a trench sidewall; (c) conformally depositing a first metal liner in the trench, wherein the first metal liner includes a bottom portion deposited over the trench bottom and a sidewall portion deposited over the trench sidewall; (d) forming at least one via in the dielectric layer adjacent to the first metal liner, wherein the via has a depth at least equal to the thickness of the dielectric layer, thereby defining a sidewall of the dielectric layer and exposing a portion of the first metal layer and a portion of said sidewall portion of the first metal liner; (e) conformally depositing a second metal liner in the via, wherein at least a portion of the second metal liner is deposited over the sidewall of the dielectric layer and over the exposed portion of the first metal layer; and (f) depositing a second metal layer over the first metal liner and second metal liner, wherein the second metal layer substantially fills the trench and the via.